1. Field of the Invention
The present invention is directed to the design and manufacture of integrated circuits. More specifically, but without limitation thereto, the present invention is directed to the design of an integrated circuit package that minimizes parasitic capacitance between metal layers in a ball grid array integrated circuit package.
2. Description of Related Art
An integrated circuit package commonly includes several electrically conductive planar layers separated from one another by electrically insulating layers. Connections between the electrically conductive layers, typically metal layers, are made by forming vias in the electrically insulating layers, typically dielectric layers, and depositing an electrically conductive material in the vias, such as copper. Circuits are formed in the metal layers by etching away a portion of the metal, for example, to form traces in routing metal layers and contacts in contact pad metal layers. The contact pads are used to make electrical connection between the integrated circuit package and a printed circuit board. Some metal layers in the integrated circuit package are used to conduct a voltage supply and others to conduct a ground return to the routing metal layers and the contact pad metal layers.